Recently, a resistance-change memory utilizing an operation principle and resistance-change material other than those of a magnetoresistive random access memory (MRAM) and phase-change RAM (PRAM) is actively developed. Such the resistance-change memory is called a resistive RAM (ReRAM). As one of the resistance-change materials used for forming the ReRAM, a metal oxide is provided. The resistance-change element using the metal oxide includes a bipolar type element and non-polar type element. The polarities of a voltage and current required for transition between the low-resistance state and high-resistance state are different in the bipolar type element and both of the positive and negative polarities can be used in the non-polar type element. The memory operation of the non-polar type resistance-change element can be performed by use of the polarity of only one direction. Therefore, it is possible to configure a cross-point cell array in which cells each having a resistance-change element and diode serially connected are arranged in intersecting points between word lines and bit lines and operate the cells.
Further, since a resistance-change memory having a resistance-change element and diode serially connected is a two-terminal memory, the memory has a feature to be easily formed to have a 3-dimensional cell structure (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2009-26867). Therefore, a two-layered structure formed by laminating two resistance-change memories, a four-layered structure formed by laminating four resistance-change memories and an eight-layered structure formed by laminating eight resistance-change memories can be attained.
The resistance of the resistance-change memory significantly varies between binary digits “0” and “1”. Specifically, the ratio of the resistances of “0” and “1” varies according to the material and is set to vary by several figures to attain a certain signal-to-noise ratio. Therefore, a current in the resistance-change memory greatly varies after the write operation and after the erase operation.
Further, the resistance-change memory is connected to each intersecting point between the bit line and word line and the resistance-change element and diode configuring the resistance-change memory share voltage VBL (for example, 3 V) applied from a bit line driver and voltage VWL (for example, zero) applied from a word line driver. Therefore, the ratio of voltages applied to the resistance-change memory is abruptly changed according to the write or erase state of the resistance-change memory. As an influence caused by this, there occurs a possibility that a current abruptly flows into the resistance-change memory when the resistance-change memory is changed from the high-resistance state to the low-resistance state.
Further, an attempt is made to increase the capacity of the resistance-change memory, miniaturize the same and reduce the cost thereof. Therefore, it is important that the resistance-change memory may have a bright future for scaling. Further, since the data input/output time is more delayed as the capacity is more increased, it is required to increase the operation speed. However, since the elements are made smaller as the memory is more miniaturized to increase the capacity, there occurs a problem that a current cannot be increased. In order to realize the high-speed operation, it is necessary to pass a larger current through the memory cell. In this case, the current value for each cross-sectional area of the element is increased. Further, if the cell array is large, the interconnection capacitances and interconnection resistances of the bit lines and word lines increase and a current caused by a component that cannot be controlled by a driver also increases although it depends on the structure of the cell array.
Thus, under the situation in which an excessively large current may flow in the cell, the performance required for the diode is attained by a structure with a withstand voltage that is highly resistive to the excessively large current. Further, in the bit line driver and word line driver, a current-limiting mechanism is provided and a measure for suppressing an excessively large current is taken. However, even if such a measure is taken, weak cells may be formed due to a variation in the manufacturing process and diodes may be destroyed. As a result, it becomes necessary to detect the destroyed diode without fail and eliminate the defective diode. Therefore, it is desired to develop a nonvolatile semiconductor memory device capable of detecting the destroyed diode without fail and a manufacturing method thereof.